The present application relates to a semiconductor device.
The losses associated with switch mode power supplies depend on the resistance of the FETs used in the circuit as well as the charge utilized by the driver during the switching event. At higher frequencies, the losses associated with charge, Qg, Qgd, etc., become large, while at high currents, the losses associated with resistance becomes large. The resistance of a device decreases with larger device width and smaller pitch (because of reduced channel and contact resistance), while the switching charge increases, which leads to a trade off between resistive and switching losses. When deciding on optimal device size, performance is generally evaluated by the R*Q product of a device. There are a few strategies for changing the RQ product. One strategy is to change the density of the two-dimensional gas (2-DEG) over the entire wafer during the formation of the III-nitride heterojunction, which leads to a penalty in drift resistance and associated RA product. Another approach is to change the 2-DEG charge in the entire region under the gate during device fabrication. Reducing the charge under the gate lowers the threshold voltage and capacitance. There are a number of ways to reduce the charge under the gate including, recess etching of the gate region, shallow implantation, and using p-type gate materials. The current processes, such as gate recessing, are difficult to control. A standard etching tool will have 10-20% variation across a wafer, which leads to a similar variation in threshold voltage across the wafer.
The invention disclosed here addresses a fundamental limitation to power management in the switch mode power supplies. Specifically, according to an aspect of the present invention, the gate charge is charged without changing the device gate width. More specifically, in a device according to the present invention, instead of reducing the charge under the gate to reduce the gate charge, the gate area is reduced by interrupting conduction under the gate which will reduce both the gate capacitance and conductivity with a smaller impact on resistance since the total ohmic contact area has not been affected. Furthermore, in a device according to the present invention, the size and the density of the ohmic contacts do not need to be adjusted as would be required when there is a blanket reduction of charge in the channel. Moreover, there will be no change in the threshold voltage of the device as may be the case when the charge is reduced in the entire region under the gate. Threshold voltage will not change since the charge density under the unaffected gate area has remained the same. Thus, the threshold voltage, gate charge, and device resistance can be tuned independently.
Advantageously, a process for fabricating a device according to the present invention will be easer compared to processes that require blanket gate charge density reduction. Moreover, the approach disclosed herein is dramatically reduces process influence on device characteristics.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.